This invention relates to phase locked loop (PLL) frequency synthesizers, and more particularly, this invention relates to phase locked loop (PLL) frequency synthesizers that generate high frequency signals for microwave and millimeter wave radar and telecommunications equipment by using an external reference clock signal.
In many telecommunication systems and electronic testing instruments, a frequency synthesizer uses a phase locked loop (PLL) circuit to generate a continuous wave signal at a precise and stable frequency. These types of phase locked loop circuits are well known to those skilled in the art, and usually include a tunable voltage controlled oscillator (VCO) having an output signal that is locked to a known reference signal by a phase detector. Any output voltage is typically related to the phase difference between a reference signal and the voltage controlled oscillator output signal. The phase detector output is coupled back to the input of the voltage controlled oscillator in a feedback loop to tune and lock the voltage controlled oscillator at a desired frequency. Thus, the phase and frequency of any final output signal from the voltage controlled oscillator has the same phase and frequency as the reference signal.
Programmable divider circuits are also used in the feedback loop between the voltage controlled oscillator and the phase detector to divide the voltage controlled output signal by a factor xe2x80x9cNxe2x80x9d. Supplemental divider circuits can divide the reference frequency by a factor xe2x80x9cMxe2x80x9d. By programming the value of the ratio xe2x80x9cNxe2x80x9d and xe2x80x9cMxe2x80x9d, the voltage controlled oscillator output signal can be made equal to a desired multiple of the reference frequency.
In some prior art frequency synthesizer devices, digitally programmable continuous wave signals are generated by phase locked loop frequency synthesizers using a programmable divider operative with the reference signal. Other frequency synthesizers generate digitally programmable, continuous wave signals using digital rate multipliers and digital dividers. Rate multiplier circuits sometimes are used to program the reference frequency by suppressing pulses of a reference signal to various program values. Spur filters are sometimes operatively connected to phase detectors and a voltage controlled oscillator to reduce spurious FM side bands. Mixers can be interposed in the feedback path to shift and extend the set of frequencies that can be generated by the phase locked loop frequency synthesizer.
It is also well known that phase locked loop frequency synthesizers are commonly used to generate high frequency sources for microwave and millimeter wave radar and telecommunications equipment. The high frequency source, also known as the Local Oscillator (LO), is used to up-convert low frequency transmitter signals to high frequency RF signals, or down-convert received RF signals to lower frequencies.
Traditionally, phase locked loop frequency synthesizers have used an accurate, relatively spur free, crystal oscillator reference typically found to be in the range of about 10 to about 100 MHz. The phase noise and spur levels of a reference clock signal are very critical, because at the output of a voltage controlled oscillator, any spurious signals are multiplied by the ratio of the voltage controlled oscillator to the phase comparison frequency. This directly impacts the performance of the closed phase locked loop circuit.
As is known to those skilled in the art, a typical phase locked loop circuit compares the phase of the divided reference clock, with that of the divided voltage controlled oscillator output signal. Any error detected in the phase between the signals is converted to a voltage that is used to correct the voltage controlled oscillator phase error. The correction voltage is applied through a filter to reduce spurious signals in the output signal, and improve the close-in, phase noise performance of the phase locked loop circuit. The loop bandwidth is typically established wide enough to reject the close-in noise of the voltage controlled oscillator, but narrow enough to reduce spurious signal levels in the signal output, thus, yielding an optimized noise spectrum that is better than that of the voltage controlled oscillator alone.
It is an object of the present invention to provide a phased locked loop frequency synthesizer that can operate with a corrupted external reference clock and generate a spur-free output.
It is yet another object of the present invention to provide a phase locked loop frequency synthesizer that overcomes the drawbacks of the prior art as described above.
The present invention provides a novel and unobvious phase locked loop frequency synthesizer and method for generating microwave and millimeter wave signals by implementing a voltage controlled, oscillator-based, phase locked loop frequency synthesizer that can operate with a corrupted external reference clock, and yet generate a very accurate and relatively spur free output signal. The present invention is advantageous for wireless terrestrial and satellite communications where the transmission and reception sources are synchronized with a reference signal that has been recovered from received communications data, which may have been corrupted with noise and spurious signals. The circuit and method of the present invention provide faster lock times than a comparable and typical frequency locked loop circuit.
The present invention generates a relatively spur free, high frequency, local oscillator signal using a corrupted reference clock signal and isolates the corrupted reference clock signal from the frequency synthesizer circuits. The present invention prevents corruption of the frequency source. The voltage controlled oscillator output frequency can be multiplied to generate higher frequency local oscillator signals with very low spurious and harmonic signals. A secondary xe2x80x9creference signalxe2x80x9d phased locked loop circuit with a narrow loop bandwidth reduces reference noise and spurious sidebands with faster lock times than a comparable frequency locked loop.
In accordance with the present invention, a phase locked loop (PLL) frequency synthesizer includes a primary phase locked loop circuit having a voltage controlled oscillator (VCO) circuit and a programmable divider circuit for establishing a voltage controlled oscillator output and a reference signal output at a divide ratio such that the outputs are equal to a common phase comparison frequency. A secondary xe2x80x9creference signalxe2x80x9d phase locked loop circuit is operatively connected to the primary phase locked loop circuit and operative for receiving and isolating an external reference signal used for the phase locked loop circuit. An oscillator generates a voltage controlled, clean reference signal. The secondary phase locked loop circuit filters and synchronizes this clean reference signal with the external reference signal for producing the reference signal output to the primary phase locked loop circuit.
In yet another aspect of the present invention, the phase locked loop (PLL) frequency synthesizer includes a filter within the secondary phase locked loop circuit for filtering the external reference signal and attenuating spurs that are outside the bandwidth of the secondary phase locked loop circuit. The filter is operative at about 2.5 Hz. The programmable divider circuit comprises chip registers that are programmable for establishing a desired divide ratio between the voltage controlled oscillator and reference signal output. A microcontroller is operatively connected to the chip registers for establishing the desired divide ratios. A frequency multiplier circuit is operatively connected to the voltage controlled oscillator for multiplying the frequency of any output signal from the voltage controlled oscillator.
In yet another aspect of the present invention, a printed wiring board supports the primary and secondary phase locked loop circuits. A plurality of isolation vias are formed preferably as through holes and isolate any circuit components of the primary and secondary phase locked loop circuits. A housing is matched as to its coefficient of thermal expansion with the printed wiring board and comprises a support member on which the printed wiring board is mounted. A housing cover has an interior surface. Channelization walls are formed by channelization on the interior surface and form isolated channels that receive individual circuit components when the housing cover is mounted on the support member. The channelization walls are juxtaposed against any isolation vias used for isolating individual circuit components when the housing cover is placed on the support plate.
A method aspect of the present invention is also disclosed and comprises the step of generating an output signal from the voltage controlled oscillator of a primary phase locked loop (PLL) circuit, which includes a programmably divided, voltage controlled oscillator output and a reference signal output at a divide ratio such that the outputs are equal to a common phase comparison frequency. The reference signal used for the phase locked loop circuit is isolated by filtering and synchronizing a clean reference signal with the external reference signal and producing the reference signal output to the primary phase locked loop circuit.